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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd16706 308/300-output tft-lcd gate driver data sheet document no. s15835ej1v0ds00 (1st edition) date published august 2002 ns cp (k) printed in japan the mark ! ! ! ! shows major revised points. description the pd16706 is a tft-lcd gate driver equipped with 308/300-output lines. it can output a high-gate scanning voltage in response to cmos level input because it provided with a level-shift circuit inside the ic circuit. it can also drive the uxga/qxga. features ? cmos level input (3.0 to 3.6 v) ? 308/300 outputs ? high-output voltage (v dd2 -v ee1 : 40 v max.) ? capable of all-on outputting (/ao) remark /xxx indicates active low si gnal. ordering information part number package pd16706n-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, please contact one of our sales representatives.
data sheet s15835ej1v0ds 2 pd16706 1. block diagram ls1 note o 1 sr1 ls1 note ls1 note clk stvr stvl oe 3 o 2 sr2 o 3 sr3 o 307 sr307 o 308 sr308 308-bit shift register ls1 note o 306 sr306 ls1 note r,/l ls1 note oe 1 ls1 note oe 2 ls2 note ls2 note ls2 note ls2 note ls2 note ls1 note /ao ls2 note ls1 note mode v ss v dd1 v dd2 v ee1 note ls1: shifts cmos level and internal level, ls2: shifts interval level and output level (v dd2 to v ee1 ).
data sheet s15835ej1v0ds 3 pd16706 2. pin configuration ( pd16706n-xxx: c opper foil surface, face-up) o 1 o 2 v dd2 v ee1 v ss stvr /ao mode co pp er v dd1 foil r , /l surface clk oe 1 oe 2 oe 3 stvl v dd1 v ee1 v dd2 o 306 o 307 o 308 remark this figure does not specify the tcp package.
data sheet s15835ej1v0ds 4 pd16706 3. pin functions pin symbol pin name i/o description o 1 to o 308 driver output output these pins output scan signals that drive the vertical direction (gate lines) of a tft- lcd. the output signals change in synchronization with the rising edge of shift clock clk. the driver output amplitude is v dd2 -v ee1 . r,/l shift direction select input input r,/l = h (right shift): stvr o 1 o 308 stvl r,/l = l (left shift): stvl o 308 o 1 stvr stvr, stvl start pulse input/output i/o this is the i/o of the internal shift register. the start pulse is read at the rising edge of shift clock clk, and scan signals are output from the driver output pins. the input level is a v dd1 -v ss (logic level). when in mode = h, the start pulse is output at the falling edge of the 308th clock of shift clock clk, and is cleared at the falling edge of the 309th clock. the output level is v dd1 -v ss (logic level). clk shift clock input input this pin inputs a shift clock to the internal shift register. the shift operation is performed in synchronization with the rising edge of this input. oe 1 to oe 3 output enable input input when this pin goes high level, the driver output is fixed to v ee1 level. the shift register is not cleared. clk is asynchronous in the clock. note that the output terminal which can be controlled by the enable signal changes refers to 4. relations of enable input and output terminal. /ao all-on control input when this pin goes low level, all driver output = v dd2 level. the shift register is not cleared. this pin has priority over oe 1 to oe 3 . this pin is pulled up to v dd1 power supply inside ic. clk is asynchronous in the clock. mode selection of number of outputs input mode = v ss or open: 300 outputs (driver output pins o 151 to o 158 are invalid.) mode = v dd1 : 308 outputs input level is v dd1 -v ss (logic level) v dd1 logic power supply ? 3.3 v 0.3 v v dd2 driver positive power supply ? 15 to 25 v. the driver output: high level v ss logic ground ? connect this pin to the ground of the system. v ee1 negative power supply for internal operation ? ?15 to ?5 v cautions 1. to prevent latch-up, turn on power to v dd1 , v ee1 , v dd2 , and logic input in this order. turn off power in the reverse order. these power up/down sequence must be observed also during transition period. 2. insert a capacitor of about 0.1 f between each power line, as shown below, to secure noise margin such as v ih and v il . v dd2 v dd1 0.1 f v ss v ee1 0.1 f 0.1 f
data sheet s15835ej1v0ds 5 pd16706 4. relations of enable input and output terminal switching is possible for 308/300 with pd16706 by the mode pin. and, the output terminal which can be controlled by the enable signal changes as follows along with this function. 308-output tcp 300-output tcp 308-output mode (mode = h) 300-output mode (mode = l) 308-output mode (mode = h) 300-output mode (mode = l) o 1 (oe 1 )o 1 (oe 1 )o 1 (oe 1 )o 1 (oe 1 ) o 2 (oe 2 )o 2 (oe 2 )o 2 (oe 2 )o 2 (oe 2 ) o 3 (oe 3 )o 3 (oe 3 )o 3 (oe 3 )o 3 (oe 3 ) o 4 (oe 1 )o 4 (oe 1 )o 4 (oe 1 )o 4 (oe 1 ) o 5 (oe 2 )o 5 (oe 2 )o 5 (oe 2 )o 5 (oe 2 ) o 6 (oe 3 )o 6 (oe 3 )o 6 (oe 3 )o 6 (oe 3 ) o 149 (oe 2 )o 149 (oe 2 )o 149 (oe 2 )o 149 (oe 2 ) o 150 (oe 3 )o 150 (oe 3 )o 150 (oe 3 )o 150 (oe 3 ) o 151 (oe 1 )v x = v ee1 o 152 (oe 2 )v x = v ee1 o 153 (oe 3 )v x = v ee1 o 154 (oe 1 )v x = v ee1 o 155 (oe 2 )v x = v ee1 o 156 (oe 3 )v x = v ee1 o 157 (oe 1 )v x = v ee1 o 158 (oe 2 )v x = v ee1 o 159 (oe 3 )o 159 (oe 1 )o 159 (oe 3 )o 159 (oe 1 ) o 160 (oe 1 )o 160 (oe 2 )o 160 (oe 1 )o 160 (oe 2 ) o 304 (oe 1 )o 304 (oe 2 )o 304 (oe 1 )o 304 (oe 2 ) o 305 (oe 2 )o 305 (oe 3 )o 305 (oe 2 )o 305 (oe 3 ) o 306 (oe 3 )o 306 (oe 1 )o 306 (oe 3 )o 306 (oe 1 ) o 307 (oe 1 )o 307 (oe 2 )o 307 (oe 1 )o 307 (oe 2 ) o 308 (oe 2 )o 308 (oe 3 )o 308 (oe 2 )o 308 (oe 3 ) remark v x is power-supply voltage of output pin o 1 to o 308 .
data sheet s15835ej1v0ds 6 pd16706 5. timing chart (r,/l = h, mode = h) clk oe 3 o 1 o 2 stvl o 1 (next dr) 3 oe 1 stvr oe 2 o 3 o 307 o 308 o 2 (next dr) /ao
data sheet s15835ej1v0ds 7 pd16706 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit logic supply voltage v dd1 ?0.5 to +7.0 v driver positive supply voltage v dd2 ?0.5 to +28 v power supply voltage v dd2 -v ee1 ?0.5 to +42 v internal operation negative supply voltage v ee1 ?16 to + 0.5 v input voltage v i ?0.5 to v dd1 + 0.5 v operating ambient temperature t a ?20 to +75 c storage temperature t stg ?55 to +125 c caution product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?20 to +75 c, v ss = 0 v) parameter symbol min. typ. max. unit logic supply voltage v dd1 3.0 3.3 3.6 v driver positive supply voltage v dd2 15 23 25 v internal operation negative supply voltage v ee1 ?15 ?10 ?5.0 v power supply voltage v dd2 -v ee1 20 33 40 v clock frequency f clk 500 khz
data sheet s15835ej1v0ds 8 pd16706 electrical characteristics (t a = ?20 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 23 v, v ee1 = ?10 v, v ss = 0 v) parameter symbol condition min. typ. max. unit high-level input voltage v ih 0.8 v dd1 v dd1 v low-level input voltage v il clk, stvr (stvl), r,/l, oe 1 to oe 3 v ss 0.2 v dd1 v high-level output voltage v oh stvr (stvl), i oh = ?40 av dd1 ? 0.4 v dd1 v low-level output voltage v ol stvr (stvl), i ol = +40 av ss v ss + 0.4 v lcd driver output on resistance r on v out = v ee1 + 1.0 v, or v dd2 ? 1.0 v 1.0 k ? pull-up resistance r pu v dd1 = 3.3 v, /ao 10 50 100 k ? pull-down resistance r pd v dd1 = 3.3 v, mode 10 50 100 k ? input leak current i il v i = 0 v or 3.6 v, except for /ao 1.0 a static current dissipation i dd1 v dd1 , f clk = 50 khz, oe 1 = oe 2 = oe 3 = l, f stv = 60 hz, no load 420 1000 a i dd2 v dd2 , f clk = 50 khz, oe 1 = oe 2 = oe 3 = l, f stv = 60 hz, no load 10 100 a i ee v ee1 , f clk = 50 khz, oe 1 = oe 2 = oe 3 = l, f stv = 60 hz, no load ?1100 ?430 a remark stv: stvr (stvl) switching characteristics (t a = ?20 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 23 v, v ee1 = ?10 v, v ss = 0 v) parameter symbol condition min. typ. max. unit cascade output delay time t phl1 c l = 20 pf, 800 ns t plh1 clk stvl (stvr) 800 ns driver output delay time t phl2 c l = 300 pf, clk o n 800 ns t plh2 800 ns t phl3 c l = 300 pf, oe n o n 800 ns t plh3 800 ns output rise time t tlh c l = 300 pf 800 ns output fall time t thl 800 ns input capacitance c i t a = 25c 15 pf timing requirements (t a = ?20 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 23 v, v ee1 = ?10 v, v ss = 0 v, t r = t f = 20 ns (10 to 90%)) parameter symbol condition min. typ. max. unit clock pulse high width pw clk(h) 500 ns clock pulse low width pw clk(l) 500 ns enable pulse width pw oe oe 1 to oe 3 1000 ns data setup time t setup stvr (stvl) clk 200 ns data hold time t hold clk stvr (stvl) 200 ns remark unless otherwise specified, the input level is defined to be v ih = 0.8 v dd1 , v il = 0.2 v dd1 .
data sheet s15835ej1v0ds 9 pd16706 switching characteristics waveform (r,/l= h, mode = h) unless otherwise specified, the input level is defined to be v ih = 0.8 v dd1 , v il = 0.2 v dd1 . t setu p clk stvr t r 90% 10% t h o ld pw c lk(h ) t f 1 305 306 2 3 t plh2 o 1 t ph l2 o 2 o 307 o 308 t plh1 stvl t ph l1 oe 1 -oe 3 t phl3 o 1 - o 308 t plh3 4 5 6 7 307 308 ? 90% 10% t tlh t th l pw oe pw c lk(l) 90% 10% 50% 90% 10% 50% 50% 50% 50%
data sheet s15835ej1v0ds 10 pd16706 7. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16706. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16706n- xxx: tcp (tab pack age) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100g (per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c: pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s15835ej1v0ds 11 pd16706 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16706 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of august 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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